Title of article :
Analysis of Error Recovery Schemes for Networks on Chips
Author/Authors :
Srinivasan Murali، نويسنده , , Stanford University Theocharis Theocharides، نويسنده , , Pennsylvania State University N. Vijaykrishnan، نويسنده , , Pennsylvania State University Mary Jane Irwin، نويسنده , , Pennsylvania State University Luca Benini، نويسنده , , University of Bologna Giovanni De Micheli، نويسنده , , Ecole Polytechnique Federale de Lausanne ، نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2005
Pages :
9
From page :
434
To page :
442
Abstract :
In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemesʹ architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Journal title :
IEEE Design and Test of Computers
Serial Year :
2005
Journal title :
IEEE Design and Test of Computers
Record number :
431608
Link To Document :
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