Title of article :
Demystifying 3D ICs: The Pros and Cons of Going Vertical
Author/Authors :
W. Rhett Davis، نويسنده , , North Carolina State University John Wilson، نويسنده , , North Carolina State University Stephen Mick، نويسنده , , North Carolina State University Jian Xu، نويسنده , , North Carolina State University Hao Hua، نويسنده , , North Carolina State University Christopher Mineo، نويسنده , , North Carolina State University Ambarish M. Sule، نويسنده , , North Carolina State University Michael Steer، نويسنده , , North Carolina State University Paul D. Franzon، نويسنده , , North Carolina State University ، نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2005
Pages :
13
From page :
498
To page :
510
Abstract :
This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rentʹs rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-μm technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-μm through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.
Journal title :
IEEE Design and Test of Computers
Serial Year :
2005
Journal title :
IEEE Design and Test of Computers
Record number :
431618
Link To Document :
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