Title of article
Raisin: Redundancy Analysis Algorithm Simulation
Author/Authors
Rei-Fu Huang، نويسنده , , MediaTek Jin-Fu Li، نويسنده , , National Central University Jen-Chieh Yeh، نويسنده , , Industrial Technology Research Institute Cheng-Wen Wu، نويسنده , , National Tsing Hua University ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2007
Pages
11
From page
386
To page
396
Abstract
To increase redundancy repair efficiency and thus final yield in embedded- memory cores, we propose Raisin, a redundancy analysis algorithm simulation tool that can calculate an RA algorithmʹs repair rate, yield, associated memory configuration, and redundancy structure. Raisin lets users easily assess and plan redundant elements and subsequently develop BIRA algorithms and circuits, which are essential for BISR of embedded memories.
Journal title
IEEE Design and Test of Computers
Serial Year
2007
Journal title
IEEE Design and Test of Computers
Record number
431759
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