Title of article
A GALS Infrastructure for a Massively Parallel Multiprocessor
Author/Authors
Luis A. Plana، نويسنده , , University of Manchester Steve B. Furber، نويسنده , , University of Manchester Steve Temple، نويسنده , , University of Manchester Mukaram Khan، نويسنده , , University of Manchester Yebin Shi، نويسنده , , University of Manchester Jian Wu، نويسنده , , University of Manchester Shufan Yang، نويسنده , , University of Manchester ، نويسنده ,
Issue Information
روزنامه با شماره پیاپی سال 2007
Pages
10
From page
454
To page
463
Abstract
This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.
Journal title
IEEE Design and Test of Computers
Serial Year
2007
Journal title
IEEE Design and Test of Computers
Record number
431769
Link To Document