A simultaneous coefficient calculation method for sinc/sup N/ FIR filters

A novel simultaneous coefficient calculation method for sinc/sup N/ filter and its application to the filter design are described. This method can be applied to any (N) stages of sinc/sup N/ filters with no degradation of coefficient accuracy. Every coefficient can be calculated by Nth-order multiple-loop accumulation of N-scaled delayed impulses. The coefficient can be obtained every clock or operation cycle because these loops are not nested but merely chained together. Sinc/sup N/ decimation filters based on this method are suitable for high-speed operation as well-known cascaded integrator-comb (CIC ) filters. If rounding or truncation is used at data-accumulation stages, they can operate faster than those in some cases. For example, the critical-path-length ratio of 32-tap single-bit-input (for delta-sigma analog-to-digital converters) sinc/sup 4/ decimation filters by this and the CIC approach is 0.714 if their outputs are rounded to 8-bit words. Unfortunately, the gate count exponentially increases in proportion to the order N. However, in some special cases (single-bit-input sinc/sup 2/ and sinc/sup 3/ decimation filters), they are comparable to the equivalent CIC filters in size.