An SRAM array based on a four-transistor CMOS SRAM cell

The static random access memory (SRAM) array discussed in this work is based on a four-transistor SRAM cell. A new method of writing the cell together with an associated array structure is proposed. The advantages are a significant reduction in power and an increase in cell reliability over previous designs. The noise margin of the cell under various conditions is investigated, as this is an effective method of designing the control mechanism of the cell.