Universal delay-insensitive systems with buffering lines

A delay-insensitive (DI) circuit is a type of asynchronous circuit that is robust to arbitrary delays in circuit elements or interconnection lines. This paper presents a new class of DI circuits of which interconnection lines have buffers that may contain multiple signals. We propose a set of three primitive circuit elements each of which has at most four lines for input or output. We prove that this set can be used to construct all valid DI circuits with buffering lines, i.e., that it is universal. Two more sets of three primitives with connectivity four are also presented, and their universality is shown. The limited number of primitives required in each universal set and the low connectivity of the primitives, as compared to previously proposed DI circuits, may facilitate efficient implementation of DI circuits in nanocomputer architectures based on asynchronous cellular automata.