A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator

This paper intends to give an insight into the potentials and tradeoffs when designing cascaded, continuous-time (CT) sigmadelta modulators. Therefore, a case study is presented considering the implementation of a 2-1-1 CT modulator. The nonideal behavior is regarded in detail and an automatic gain-error cancellation is presented. Finally, a circuit board implementation is presented, which has been chosen to verify the automatic error correction. It turns out that despite a more critical behavior than in the discrete-time (DT) case, cascaded CT modulators have the potential, to realize high bandwidth, high resolution analog-to-digital (A/D) converters in future integrated designs.