Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies

As scaling of silicon devices continues at an aggressive pace, the problems associated with it are becoming more and more evident. With “short-channel effects” already in the way of scaling, interest has shifted to the possible use of nonsilicon molecular devices for circuit implementation. Carbon nanotube has emerged as a promising candidate. However, molecular devices such as carbon nanotube field-effect transistors (CNFETs) with their super-scaled dimensions and high current densities would increase the power density on chip and reasonable predictions estimate that they would far exceed the maximum power density limitation [1] . This paper explores the use of energy-recovery techniques in molecular CNFET based digital circuits and demonstrates how they can alleviate the power density problem in such circuits.