Crosstalk delay analysis of a 0.13-(mu)m node test chip and precise gate-level simulation technology

The impact of crosstalk on delay was examined by measuring a test chip manufactured with a 0.13-(mu)m node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: 1) consideration of degradation change dependent on relative signal arrival time over a wide range; 2) static timing analysis-based operation; and 3) quantitative estimation of the degradation accumulation caused by multiple aggressors. A candidate for such simulation technology is provided, and its highly precise characteristics are demonstrated through comparisons between measurement and simulation. In a test structure with two aggressors, the maximum error between the measured and simulated degradation was reduced to less than one-sixth of that with a conventional method.