Application of 45 nm VLSI Technology to Design Layout of Static RAM Memory

This paper present area efficient layout design for static RAM memory using 45nm VLSI technology VLSI Technology includesprocess design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design. The proposed PLL is designed using 45 nmCMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical descriptionlevel. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. Theeffective gate length required for 45 nm technology is 25nm. Low Power (0.211mwatt) , high speed static RAM area efficient chip isdesigned using 45 nm VLSI technology