• Title of article

    HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter

  • Author/Authors

    Anis Boudabous، نويسنده , , Ahmed Ben Atitallah، نويسنده , , Lazhar Khriji، نويسنده , , Patrice Kadionik، نويسنده , , and Nouri Masmoudi، نويسنده ,

  • Issue Information
    روزنامه با شماره پیاپی سال 2010
  • Pages
    5
  • From page
    70
  • To page
    74
  • Abstract
    A new code sign implementation of vector median rational hybrid filter based on efficient hardware/softwareimplementation is introduced and applied to colour image filtering problems. This filter is used essentially to removeimpulsive and Gaussian noise in colour images. In our design we start by implementing the software solution in system onprogrammable chip context using NIOS-II softcore processor and )Clinux as operating system. We evaluate the executiontime of the whole filtering process. Than we add a hardware accelerator part. This latter is implemented using fast parallelarchitecture. Compared to the software solution results, the use of the hardware accelerator improves clearly the filteringspeed and maintains the good filtering quality as shown by simulations
  • Keywords
    filtering , Co-design , FPGA implementation , NIOS-II processor , SoPC
  • Journal title
    The International Arab Journal of Information Technology (IAJIT)
  • Serial Year
    2010
  • Journal title
    The International Arab Journal of Information Technology (IAJIT)
  • Record number

    668782