A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs

A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller inprogrammable logic devices, and field programmable gate array devices, is suggested. The test procedure involves; theconfiguration of programmable logic devices or field programmable gate array device, the application of test vectors, andfinally the verification of the response. These steps are repeated with two different configurations of the device under test, toensure high faults coverage. Both the configuration, and the application of test vectors, is performed through the joint testaccess group port of the device under test. The parts of the boundary scan circuit and the type of faults which are covered arementioned