Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs

Problem statement: The S-Box transformation is a computationally intensive and important operation of the Advanced Encryption Standard (AES). Approach: This study presents the comparative study between reduced Residue of Prime Numbers and Galois Filed GF (28) based S-Boxes using Virtex-5 and Virtex-6 FPGA devices. The implementation of S-Boxes is done using Very High speed integrated circuit Hardware Description Language (VHDL). Results: The results obtained from Virtex-6 FPGA show that the proposed method runs at a clock frequency of 0.785ns, which is three times faster than S-Box based on Galois Filed GF (28). Conclusion: The reduced version of the S-Box based on prime number shows promising results as compared to Galois Field GF (28) based S-Box, which could be used in AES to increase its complexity and add more confusion.