Delay-insensitive logic in software-defined radio applications

This article describes how one of the fundamental hardware stumbling blocks to fully achieving software-defined radio, high speed, and wide dynamic range data conversion can be overcome with the selective application of a class of asynchronous logic referred to as delay-insensitive logic. Certain characteristics of delayinsensitive logic can be exploited using unique architectures to reduce digital switching noise and whiten the noise signature. The result is enhanced mixed mode performance in highly integrated systems. The performance enhancement of an interpolating digital-to-analog converter is presented as a specific example. Because the concept of delay-insensitive logic is not familiar to most engineers, a brief introduction to the general concept is given.