A Low Power, Glitch Free Programmable Divider in 0.18µm CMOS Technology

A low power programmable frequency divider is proposed in this paper which is appropriate for WLAN applications. Multi- modulus architecture in dynamic logic with the minimum number of transistors is designed in 0.18µm CMOS technology. By using mixer, bandpass filter and switches, the divide ratios improved to 18. A technique is implemented in the dynamic 2-3 programmable divider cell for decreasing the glitches which leads to low power consumption. Based on simulation results it works up to 5GHz, with the average power about 37nW. Under a supply voltage of 1.8V, the total chip area of the multi- modulus programmable divider is 3100µm2.