A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-(mu)m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve highspeed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes ~31 mA at V/sub DD/=1.8 V.