Author/Authors :
J.، Abrams, Lewis نويسنده , , N.، Richardson, نويسنده , , Huang، Lun Bin نويسنده , , R.، Hossain, نويسنده , , T.، Zounes, نويسنده , , N.، Soni, نويسنده ,
Abstract :
A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.
