An analytical expression for the input impedance of a fractal tree obtained by a microelectronical process and experimental measurements of its non-integral dimension

The great interest centered around the materials of fractal structure in recent years led us to investigate the electrical behavior of metallic samples having “fractal tree” patterns. The analysis of these structures is carried out on a Metal-Insulation-Semiconductor (MIS) type of capacitor with one of its plates presenting a fractal dimension. In this article, an analytical expression of a fractal tree-input impedance at different iteration levels is developed showing that an interesting simplified version can be deduced at low frequencies at which the structural behavior is purely capacitive. This expression suggests an extraction method of the structural non-integral dimension from impedance measurements of the object at different iteration levels. The simulations and the measurements carried out assured us of the validity of the proposed model and highlighted the frequential evolution of the fractal structure-impedance.