Fault diagnosis in electronic circuits based on bilinear transformation in 3-D and 4-D spaces

Presents two new methods of fault localization and identification in linear electronic circuits, based on a bilinear transformation in multidimensional spaces. The conventional bilinear transformation maps changes of circuit component parameters p/sub i/ into a family of p/sub i/-loci on the complex plane. The loci can be used for fault diagnosis as well as parametrical identification measurements of objects modeled by electrical circuits. The bilinear transformation method proposed by Martens and Dyck [1972] was based on the family of p/sub i/-loci on a plane. It was difficult to implement this method (called here the two-dimensional method) in practice because frequently p/sub i/-loci are situated too close to each other or superimpose one on another. The authors propose a new approach based on transferring p/sub i/-loci from a plane to three-dimensional (3-D) or four-dimensional (4-D) spaces. Distances between p/sub i/-loci in space are greater. This fact leads to better fault resolution and robustness against the influence of component tolerances and measurement errors. This approach also gives the possibility of creating p/sub i/p/sub j/-surfaces or hypersurfaces, which can be used for double-fault diagnosis or two-parameter identification measurements. The 3-D and 4-D algorithms of single- and double-fault diagnosis, and experimental verification of the 4-D method and the implementation of the 4-D method in a neural network are described.