Designing of processor-time optimal systolic arrays for band matrix-vector multiplication

This paper describes the procedure for synthesizing processor-time optimal linear (1D) systolic arrays for band matrix-vector multiplication. The procedure is based on data dependence approach. By the described procedure, three different systolic arrays, denoted as S1, S2 and S3, are obtained. The first two are obtained by the orthogonal directions. The array S3 is a bidirectional linear array of Kungʹs type. The procedure enables us to obtain optimal bidirectional 1D systolic array where data streams enter the array in consecutive time instances which leads to decreasing of execution time and increasing of PEsʹ utilization