Simulation of oxide trapping noise in submicron n-channel MOSFETs

Carrier trapping via tunneling into the gate oxide was implemented into a partial differential equation-based semiconductor device simulator to analyze the 1/f-like noise in silicon MOSFETs. Local noise sources are calculated using the carrier tunneling rates between trap centers in the oxide and those at the interface. Using the Greenʹs transfer function approach, noise contributions from each node in the oxide mesh to the overall noise at the specified contact terminals are simulated. Unlike traditional 1/f noise analyses in MOSFETs, the simulator is capable of simulating noise for a wide range of bias voltages and device structures. The simulation results show that for an uniformly doped channel, the region in the oxide above the pinch-off point in saturation is most critical for low frequency noise generation while for a graded channel device the source side of the gate oxide region becomes important. By comparing the simulation results with the measured noise data, the oxide defect density in the noise producing regions can be profiled.