Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-(mu)m and 0.25-(mu)m CMOS with different pixels array sizes. For 2-(mu)m SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-(mu)m CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now.