Timing constraints for domino logic gates with timing-dependent keepers

Low threshold voltage (V/sub t/) can be applied to domino logic to improve the performance in dual threshold voltage technology. Then, the keeper transistor should be up-sized to compensate for reduced noise margin due to the significant subthreshold current of low V/sub t/ transistor. However, a large keeper transistor degrades performance. To resolve the tradeoff between performance and noise margin, the authors propose a new domino logic which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of the proposed domino logic yields optimal timing conditions wherein a contention-free skew-tolerant window is maximized. A broad range of the skew-tolerant window connotes robustness against noise and design parameter variations, while reduced contention between keeper and evaluation NMOS transistors ensures high-speed switching. The authors show that the dual keeper structure increases noise tolerance and delay logic gates fortify signal skew tolerance. Simulation results verify that the proposed domino logic is robust to noise and signal skew while presenting high performance and power efficiency.