Yield prediction by sampling IC layout

This paper reports a survey sampling-based methodology for critical area and other property estimates of IC layout. A software implementation of the method, Edinburgh yield estimator sampling (EYES) is presented. The EYES tool implements the survey sampling-based methodology for critical area estimation enabling the yield prediction of ULSI chips. The method requires an analysis of only a small fraction of the chip layout. As a result the practical application of the technique is not limited by the size of the chip, or the design hierarchy. The EYES system is able to process non-Manhattan layout. This enables yield predictions in a reasonable time for even the largest state-of-the-art chips, using modest computing resources