EMI-noise analysis under ASIC design environment

Electromagnetic compatibility (EMC) has become more and more important in designing electronic systems. Although electromagnetic radiation itself mainly occurs from off-chip conductors, the ultimate noise source is in LSI chips. Among the noise distribution paths, the power-line conducting noise is the most significant source of electromagnetic interference (EMI)noise caused by LSIs. This paper introduces an EMI-noise analysis method suitable for application-specific integrated circuit design environment especially focusing on the power-line conducting noise. Modeling method for power network and switching activity, simulation flow, and experimental results are presented. Experimental results show that our modeling methodology estimates capacitance values with sufficient accuracy and reproduces the relative differences in EMI-noise levels.