Title of article :
Interconnect sizing and spacing with consideration of coupling capacitance
Author/Authors :
Koh، Cheng-Kok نويسنده , , J.، Cong, نويسنده , , Pan، Zhigang نويسنده , , L.، He, نويسنده ,
Issue Information :
روزنامه با شماره پیاپی سال 2001
Abstract :
This paper studies interconnect sizing and space (ISS) problem with consideration of coupling capacitance for performance optimization of single or multiple critical nets. We introduce the formulation of symmetric and asymmetric wire sizing. We develop efficient bound computation algorithms for ISS optimization and prove their optimality under general interconnect resistance and capacitance models. Our experiments show that our algorithms are very effective and obtain significant performance improvement compared to previous wire-sizing/spacing algorithms
Journal title :
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Journal title :
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS