Integration of a TiN barrier layer formed by rapid thermal annealing in a 1 μm CMOS process

This paper describes the integration of a TiN barrier layer formed by rapid thermal annealing (RTA) in a twin-well double-metal 1 μm CMOS process with poly-Si gate. The formation of TiN by RTA of sputter-deposited Ti was investigated in a temperature range between 600°C and 900°C in N2 or NH3 atmosphere. A double-step RTA at 650°C NH3 and 800°C N2 yielded good barrier behaviour, but we observed that this combination led to field inversion. Better results in terms of process integration were obtained with a single-step RTA between 750°C and 850°C in N2. Parameter tests showed that the TiNTiSi2 contacts had low contact resistances to N+- and P+-silicon and no leakage current after six H2 annealing cycles (420°C). We also tested the stress migration and electromigration of the TiNTiSi2 contacts and the TiNAlSiCu Metal 1 interconnects. The influence of the RTA temperature on device reliability and yield was studied. It has been demonstrated that the device and contact reliability of this RTA barrier process is very good.