Advanced metallization technology for 256M DRAM

An advanced three-level interconnect technology for 0.25 μm design rule has been developed for a 256M DRAM process, that provides increased circuit density, improved manufacturability and reduced cost. The process includes a polycide gate stack, self-aligned bitline contacts, a tungsten bitline, an Al-stitched wordline for the second level of metal and an Al global wiring level. Chemical-mechanical polishing (CMP) has been extensively used to improve planarity which increases the process window for lithography and etch. This metallization concept has been implemented on a 256M DRAM within the framework of a process architecture including a BuriEd STrap (BEST) trench memory cell and shallow trench isolation (STI). Five novel processes are discussed in detail. A self-aligned array contact using a highly selective etch process for SiO2Si3N4, low ∈ IMD of fluorosilicate glass (FSG) deposited in a dual-frequency plasma CVD process (D-FSG) in comparison to HDP CVD and an alternative low-cost monolithic stud-wire concept using high temperature Al-PVD and planarization by a non-corrosive Al CMP. The “Dual Damascene” interconnects show improved electromigration resistance compared to RIE-patterned Al-sandwich structures on W studs.