Inter-metal dielectric planarization process for 0.35 μm multilevel interconnection devices

A high inter-metal dielectric (IMD) planarization degree is requested in VLSI device manufacturing to avoid process degradation with increasing number of interconnection layers. In this work an IMD planarization process based on the use of spin on glass (SOG) for gap filling followed by SOG partial etch back (PEB) is presented. The main advantage of this process is its capability to provide at the same time long range planarization with the ability to completely fill spaces between metal stripes 0.4 μm wide with an aspect ratio (AR) greater than 2. These results were obtained using a first oxide tapering process and making use of a single thick SOG coating followed by PEB. The planarization performances make the process suitable for the production of three and five metal level interconnection devices of 0.35 μm technology, keeping at the same time the process simple, cheap and highly repeatable.