A highly reliable, low cost 0.5 μm three level tungsten metallization

A pure tungsten metallization, which uses the refractory metal in contacts, vias and interconnects, has been successfully integrated into a three level 0.5 μm complementary metal-oxide-semiconductor (CMOS) process. Each metallization level was fabricated by CVD of tungsten onto TiTiN and, after standard i-line lithography, a two step metal patterning using SF6Ar and Cl2/N2/BCl3, respectively. This metallization approach is compared with the standard tungsten plug filling combined with AlSiCu interconnects. Although the W-line resistance is found to be a factor of three higher than the AlSiCu lines, only marginal impact on chip performance is predicted for local interconnects by simulation. Due to the reduced number of interfaces, Kelvin resistances measured for the tungsten metallization are even lower than for the reference. Highly accelerated wafer level stress investigations with a current density of 2 MA/cm2 revealed no failure of the W lines after 200 h stressing even at temperatures up to 420°C, indicating at least a 200 times improved lifetime. Thus, this metallization is best suited for high temperature or high current applications. A cost comparison for various metallization schemes indicates that the total process cost for the reference is about 50% higher than for the tungsten metallization. Furthermore, this metallization is not only fabricated via a simple and low cost process, which avoids several process issues typically associated with the reference. It also offers the possibility of higher temperature budgets after metallization.