Dielectric property of ferroelectric-insulator-semiconductor junction

The voltage dependence of the high-frequency capacitance of a metal-ferroelectric-insulator-semiconductor (MFIS) structure is analyzed by relating the potential profile to the dielectric hysteresis of the ferroelectric thin film. About one hundredth of the dielectric polarization of ferroelectric ceramic PZT is enough to control the Si surface potential for ferroelectric gate FET memory, and large coercive force is required to obtain enough voltage window. MFIS structures using Bi-layer-structured ferroelectric thin films are also studied from experimental viewpoint. SrBi,Ta,O, and Bi,Ti,O, thin films have been prepared by laser ablation method on both Pt sheet and Si wafers at low temperatures of 400-500°C. SrBi,Ta,O, thin films have a good (105) preferential orientation, and Bi,Ti,O, thin films have (117) and c-axis orientations on these substrates. D-E hystereses are obtained in SrBi,Ta,O, and Bi,Ti,O, thin films prepared on Pt sheet, and are enough to control the Si surface potential. Ferroelectric film-SiO,-Si structures show good C-V hysteresis curves owing to the Si surface potential controlled by the D-E hysteresis.