Low-temperature dopant activation technology using elevated Ge-S/D structure

Dopant activation annealing of an elevated Ge-S/D structure formed on Si was investigated for application in advanced CMOSFET fabrication. Due to the low melting point of Ge, dopant activation was observed below 600 8C. However, the low temperature annealing process resulted in high reverse-bias p–n junction leakage. A thermal process budget of 900 8C, 60 s was found to be the minimum necessary for achieving low junction leakage. The location of the junction after the 900 8C annealing can be as shallow as 20 nm beneath the original Si interface for both pþ/n and nþ/p diodes. # 2003 Published by Elsevier B.V.