A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 (mu)A/(mu)m for the off-current of 100 nA/(mu)m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.