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Développement dיun outil de synthèse analogique pour les systèmes à courants commutés utilisant VHDL-AMS

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The purpose of this contribution is to develop an Analogue-Synthesis tool for switched current systems. This tool will allow the user to develop and optimize the system to designfrom specifications with a high level simulation. First, a block diagram ofthe design jlow which is going to be used to simulate and characterize SI system is presented. Second, a cell library was developped. It contains VHDLAMS descriptions for two basic memory cells (A and AB Class). This library helped modeling first and second order Sigma-Delta modulators which led to perform a spectrum analysis and achieve a characteristic study.

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