چكيده لاتين :
This paper describes a VHDL implementation of a behavioural model for novel
programmable resolution analog to digital converters (ADCs). This architecture uses the
dichotomic method in the conversion. The goal for using this VHDL description is to validate
the algorithm conversion and facilitate the synthesis of the digital part. In this example it
includes digital control ofdichotomic method. The structure ofthe converter is composed ofa
reference voltage generator, a programmable gain amplifier and a low resolution ADC. An
ADC of l Z-bits has been modeled and simulated using VHDL. The Static Test Ramp Method
is appliedfor the testing ofthe IZbitsADC models. Also, we show how the analog parts affect
the linearity ofADC. Static parameters such as INL and DNL are determined andpresented.
