An FPGA Based Implementation of Forward Automatic Order Selection Processor

In this study, a new Constant False Alarm Rate processor is investigated with proposed process termed as Forward Automatic Order Selection Ordered Statistics Detector (FAOSO), which does not require any prior information about the number of interfering targets. The proposed architecture has been implemented on a Field Programmable Gate Array (FPGA). After simulating the HDL model of processor, it is implemented using ISE Navigator 6.3i software. The target device for implementation is XC2v300e-6fg456 Virtex-II device .The implemented processor using this technique has been tested using Monte Carlo simulation in presence of eight interfering targets. However, the hardware synthesis results and timing analysis are reported and the implementation process and the study shows clearly that how this digital tool is excellent due to its high reliability and flexibility