Enhancing Power Supply Rejection of Low-Voltage Low-Dropout Voltage Regulators Using Bulk Driven PMOS

Enhancing Power Supply Rejection of Low-Voltage Low-Dropout Voltage Regulators Using Bulk Driven PMOS

In this paper a low-voltage low-dropout (LDO) regulator is presented in which the power supply rejection (PSR) is increased by properly driving the bulk of the PMOS passtransistor. A signal proportional to the supply noise is injected to the bulk of the PMOS transistor so that the impact of supplynoise on the output voltage coming from other paths is cancelled. Using this technique the PSR of the regulator is increased by approximately 20 dB over a wide frequency range. The supplyvoltage of the prototype regulator is 1.2 V and the output voltage is 1V. It is designed in 0.18μm CMOS technology and provides acurrent of 50 mA to the load