Wide-Range, Low- Jitter Frequency Synthesizer Using Common Mode DC Setting Strategy in VCDL

Wide-Range, Low- Jitter Frequency Synthesizer Using Common Mode DC Setting Strategy in VCDL

A low jitter, multi-phase delay-locked loop based frequency synthesizer for wide locking range with simple and open loop phase detector is proposed. Dead-Zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of delay cells is modified, given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Moreover the results show that the dead-zone of the phase detector and jitter of the outputs are reduced as well. Worst-Case simulation results in post-layout simulations for all corners, using the BSIM3 model of 0.18um CMOS process when the supply voltage is subject to around 30mvolts peak-to-peak noise disturbances confirm that DLL loop can provide phases in frequency range of 20MHZ to 200MHz, consuming total power of 6.8mW at 200MHz. The designed chip occupies an area of 0.06 mm2