A Single-to-differential Low Noise Amplifier design Exploiting Differential Active inductor in 0.18μ𝒎 CMOS Technology

In this paper a single input, differential output low noise amplifier is proposed. The LNA utilizes a noise reduction technique to improve the noise performance. It is composed of two stages. The first stage is a CS cascode parallel with CG cascode stage and the second stage is composed of differential CS cascode amplifier. A differential active inductor is used as loads of the differential amplifier to increase the tune-ability of the output frequency range and decrease the chip size. The proposed single -to- differential amplifier by using the noise reduction technique and gm-boosting technique present lower noise figure in comparison with the other single to differential LNAs. The S-to-D-LNA is simulated with Cadence Spectra using 0.18um CMOS technology. For the selected frequency of 1.5, 2 and 2.4 GHz, the simulation results show the S21 of 12.8, 32.4 and 35.4 dB, S11 of -19,14.2, -12.4 dB, S12 of -63.8, -64.4 and -48 dB and NF of 3.4, 3.9 and 4 dB, respectively. The power dissipation is 9.8 mw from 1.8 V DC power supply.