A 3.48ps Jitter @ 1.45GHz Fully Differential Dual band DCO with a new Reconfigurable Delay Cell

In this paper a dual band differential DigitalControlled-Oscillator (DCO) with a reconfigurable delay cell in each four stages of digitally controlled ring Oscillator is proposed. The bands switching will done by a digital mode select bit. Each band will controls by 6 bit codes and varies in a 50MHz band width. Band variations occurs by changing the sizing of the current tails of Source-Coupled-Logic (SCL) based delay cells. A new SCL based delay cell is used which has a reconfigurable structure. The structure transformation influence on power and delay path. But in each band the power consumption profile has a monotonic changes. Fully differential oriented structure ensures low jitter design, 6.04ps @505.1MHz in lower band and for upper band 3.48ps @1.45MHz. The simulations are in 180nm CMOS technology. First band with select bit 0 has frequency range [455.2505.1] MHz and consumes power 1.98mW @455MHz. Upper band in select bit 1 position with frequency range of [1.39-1.45] MHz has power consumption , 9.7mW @1.39GHz. Small signal model for delay calculation and circuit analysis are done for validity of results. Also, Monte Carlo and central frequency disturbance are shown the acceptable operation of the proposed circuit.