VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m) using Dual Bases

This paper presents the efficient VLSI architecture for bit parallel systolic multiplication over dual base for trinomial and pentanomial in GF(2m) for effective use in RS decoders. This architecture supports pipelining. Here irreducible trinomial of form p(x) = xm + xn + 1 and pentanomial of the form p(x) = xm +xk+2 + xk+1 +xk+1 generate the fields in GF(2m). For ECC algorithms, NIST recommends the five reduction polynomials which are either trinomial or pentanomial. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. For trinomial, the systolic structure of proposed bit parallel dual multipliers requires only m2 two inputs and gates and at most (m2-1) two inputs EXOR gates. For pentanomial, it requires only m2 two inputs and gates and (m2+3m-3) two inputs EXOR gates. The proposed multipliers have clock cycle latency of m. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. This architecture can also operate over both the dual-base and polynomial base.