Chip Master Planning: An Efficient Methodology to Improve Design Closure and Complexity Management of Ultra Large Chips

Mis-prediction is a dominant problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in failing the design cycle convergence. In this paper, a new planning methodology is presented in which a masterplan of the chip is constructed in early levels of physical design and the rest of succeeding physical design stags operate considering this masterplan. The proposed planning design flow is used to wire planning and buffer resource planning in order to compare with conventional contributions. Experimental results show the considerable improvements in terms of performance, timing yield and buffer usage.