Latency Optimizing Overlay Network For Partitioning Mesh Network-on-Chips Into Multi-Die Systems

Partitioning a large mesh network-on-chip into a system of multiple interconnected smaller dies to achieve yield or cost improvement poses significant challenges with respect to preserving bandwidth and latency. The present work seeks to mitigate these adverse effects, with particular emphasis on latency, through the implementation of an ring type overlay network retrofitted to the partitioned sub-dies. The feasibility of the proposed scheme when using partition sizes in the range of 64 mm2 has been verified for 200 MHz non-pipelined operation in 90 nm technology, with an indicated potential of up to 630 MHz performance being achievable with a suitably designed on-die interconnect. A static analysis based on 25 router nodes per sub-die indicates an improvement in system-level latency of up to 53 % for 16 die configurations.