Parallel Quick Sort using Shared Memory Architecture

This paper presents quick sort scheme for special purpose parallel architectures such as sorting networks in cooperation with general purpose parallel architectures such as SIMD computers. In general, access to the shared memory of a tightly coupled system through interconnection network is time consuming. This problem can be alleviated by minimizing the number of accesses to shared memory with the help of parity strategy. This strategy uses local memory of virtual processor to reduce the memory access via interconnection networks. An abstract of the proposed architecture has been designed which makes it independent of the features of machine like number of processors, architecture and interconnection among the processors. From results it has been observed that by reducing the communication through the network a performance improvement is achieved.