Author/Authors :
Mercedeh Sanjabi Electrical, Computer and Biomedical Eng. Dept. - Qazvin Branch Islamic Azad University Qazvin, IRAN , Ali jahanian Electrical and Computer Eng. Dept. - Shahid Beheshti University, G. C. Velenjak, Tehran, IRAN , Saba Amanollahi Electrical and Computer Eng. Dept. - Shahid Beheshti University, G. C. Velenjak, Tehran, IRAN , Negar Miralaei Electrical and Computer Eng. Dept. - Shahid Beheshti University, G. C. Velenjak, Tehran, IRAN
چكيده لاتين :
Simulated annealing is known as a widely used
algorithm for complex and nonlinear combinatorial optimization
problems. This technique has been applied to variety of the
problems such as VLSI cell placement. However, simulated
annealing placement requires long execution time to brows the
search space and find the near-optimal solution. There were
many attempts to parallelize it on multi-processor systems
but addressed algorithms results in poor speedup due to
considerable communication overhead between the processors.
In this paper, we proposed a new parallel Simulated Annealing
based on multi-core systems with very low communication
overhead. Experimental results show the speedup of the
proposed algorithm is improved by 32% on average without
considerable quality degradation.
