شماره ركورد كنفرانس :
3537
عنوان مقاله :
Modeling, Evaluation and Mitigation of SEU Error in Three-Dimensional FPGAs
Author/Authors :
Mona Nassehi Osgooi Dept. of Electrical, IT and Computer Eng. - Qazvin Branch Islamic Azad University Nokhbegan Blv., Qazvin, IRAN , Ali Jahanian Dept. of Electrical and Computer Eng. - Shahid Beheshti University, G. C. Velenjak, Tehran, IRAN , Hamid. R Zarandi Dept. of Computer Eng. - Amirkabir Univ. of Tech. (Tehran Polytechnic) Hafez St., Tehran, IRAN
كليدواژه :
Layer assignment , Single event upset , Three dimensional FPGA
عنوان كنفرانس :
شانزدهمين همايش بين المللي معماري كامپيوتر و سيستم هاي ديجيتال
چكيده لاتين :
SEU error which is made by various radiations
affects the signal integrity of nano-scale circuits, especially
for future ultra-large and complex circuits. In this paper, we
proposed a SEU error model for three-dimensional FPGAs and
evaluate the SEU error of 3D-FPGAs based on the proposed
model and then compare the SEU error rate of 3D-FPGAs
with 2D-FPGAs. Moreover, we proposed a 3D layer assignment
for improving SEU error possibility on three-dimensional
FPGAs. The experimental results show that SEU error rate
and critical delay decreases about 67% and 13.1% on 4 layers
3D-FPGA compared with 2D-FPGAs, respectively. In addition,
the proposed layer assignment improves the possibility of SEU
error of 3D-FPGAs up to 6.5% for large FPGA circuits.
