شماره ركورد كنفرانس :
3537
عنوان مقاله :
A Novel High-Speed Low-Power Binary Signed-Digit Adder
Author/Authors :
Somayeh Timarchi Department of Electrical and Computer Engineering - Shahid Beheshti University, Tehran, Iran , Parham Ghayour Department of Electrical and Computer Engineering - Shahid Beheshti University, Tehran, Iran , Asadollah Shahbahrami Department of Computer Engineering - University of Guilan, Rasht, Iran
كليدواژه :
FPGA , high-speed low-power arithmetic , binary signed digit number system , Redundant addition , VLSI
عنوان كنفرانس :
شانزدهمين همايش بين المللي معماري كامپيوتر و سيستم هاي ديجيتال
چكيده لاتين :
Addition is one of the most important arithmetic
operations in digital computation. Optimization of adders’ speed,
power, and area is a challenging task. To this end, redundant
number system has been proposed in the literatures. In this
paper, we propose a new redundant binary signed-digit adder
that not only utilizes specific encoding for the input operands,
but also uses a new efficient adder structure. Using this
technique we can generate low power signed digit adders that
perform fast additions. The comparisons show delay, power and
area reduction both on FPGA and Synopsys Design Vision tool.
