Fault-Tolerant Assessment and Enhancement in the Reconfigurable Network-on-Chip

This paper suggests a mechanism to increase the fault tolerance of switches which are used in the reconfigurable network-on-chip. The focused reconfigurable network-on-chip is composed of some simple switches having been inserted between adjacent routers in the mesh topology in order to increase the performance. In other words, the routers which communicate the most are connected to each other directly instead of connecting to each other through intermediate routers. The structure implements the topology based on traffic pattern of the application. Therefore, the latency and power consumption would decrease. Each switch is composed of SRAM cells in order to connect or disconnect the paths. First, the effects of SEU faults were investigated on the SRAM cells. The simulation results show that about 90% of fault injection experiments would fail. Thus, a fault tolerant switch in which the unprogrammed paths would be used for making redundant paths would be proposed. Finally, applying this technique would decrease the failure rate to 64%.