A Review on the Development of GAN Techniques in convolutional Neural Networks and its implementation on FPGA accelerator

Recently, the growth of convolutional neural networks in various scientific fields can be seen dramatically. The use of various software and hardware techniques in advancing this process provides the platform for increasing research and finding different solutions to increase the efficiency and optimization of this method. One of the important techniques in the field of neural networks is the Generative Adversarial Networks (GAN) and its implementation on FPGA accelerators. In this paper, we will provide an overview of the growth process of convolutional neural networks with using GAN technique and its implementation on FPGA accelerator over two years. In this series we intend to follow some of the most primitive projects starting almost 2017 and by the end of 2018, where significant progress can be made. In this work, we review five papers, the first of which is presented in 2017 and the other four in 2018. The method of comparing these articles is characterized by four distinct perspectives: Optimal utilization of accelerator resources, application of specific techniques, analysis of generated data, and finally the speed of execution in FPGA-based systems is a requirement. Finally, we discuss the advantages and disadvantages of these designs to optimize and improve their performance.